LDO is a linear regulator. The linear regulator uses a transistor or FET running in its linear region to subtract the excess voltage from the applied input voltage to produce a regulated output voltage. The so-called voltage drop voltage, is the regulator to maintain the output voltage in its rating up and down within 100mV required input voltage and output voltage difference between the minimum. The output voltage of the LDO (low voltage drop) regulator is usually used as a power transistor (also known as a transfer device) as a PNP. This transistor allows saturation, so the regulator can have a very low voltage drop voltage, usually about 200mV; compared with the use of NPN composite power transistor traditional linear regulator voltage drop of about 2V. The negative output LDO uses NPN as its delivery device, and its operating mode is similar to PNP devices that are output LDOs.
The updated development uses CMOS power transistors, which can provide the lowest voltage drop voltage. Using CMOS, the only voltage drop across the regulator is caused by the ON resistance of the power supply load current. If the load is small, the pressure drop in this way is only tens of millivolts